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FireLink USB
82C862 Dual Controller Quad Port USB Preliminary Data Book CONFIDENTIAL
912-2000-030 Revision 1.0
Copyright Copyright (c) 1999 OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, manual, or otherwise, without the prior written permission of OPTi Inc., 1440 McCarthy Blvd. Milpitas, CA 95035.
Disclaimer OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to revise the design and associated documentation and to make changes from time to time in the content without obligation of OPTi Inc. to notify any person of such revisions or changes. Trademarks OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respective holders.
OPTi Inc.
1440 McCarthy Blvd. Milpitas, CA 95035 Tel: (408) 486-8000 Fax: (408) 486-8001 WWW: http://www.opti.com
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FireLink USB 82C862
TABLE OF CONTENTS
1.0 2.0 3.0
FEATURES ......................................................................................................................................................................1 OVERVIEW ......................................................................................................................................................................1
SIGNAL DEFINITIONS ....................................................................................................................................................3 3.1.1 Terminology/Nomenclature Conventions..............................................................................................................3 3.2 NUMERICAL PIN CROSS-REFERENCE LIST .........................................................................................................................5 3.3 SIGNAL DESCRIPTIONS ....................................................................................................................................................6 3.3.1 Clock and Reset Interface Signals .......................................................................................................................6 3.3.2 PCI Bus Interface Signals.....................................................................................................................................6 3.3.3 USB Interface Signals ..........................................................................................................................................8 3.3.4 Host Controller shared signals: PME#, SMI#, REQ#, GNT# ................................................................................9 3.3.5 Legacy and Interrupt Interface Signals.................................................................................................................9 3.3.6 Power and Ground Pins .....................................................................................................................................10 3.3.7 Strap Options .....................................................................................................................................................11
4.0 FUNCTIONAL DESCRIPTION.......................................................................................................................................13 4.1 UNIVERSAL SERIAL BUS (USB) ......................................................................................................................................13 4.2 PCI CONTROLLER.........................................................................................................................................................14 4.3 CLOCK GENERATION .....................................................................................................................................................15 4.4 POWER MANAGEMENT FEATURES...................................................................................................................................15 4.4.1 Putting FireLink into USBSuspend State ............................................................................................................15 4.4.2 Powering Down the USB I/O Cells .....................................................................................................................15 4.4.3 Stopping the 48MHz USB Clock.........................................................................................................................15 4.4.4 Using CLKRUN# ................................................................................................................................................15 4.4.5 Stopping the Internal PCI Clocks........................................................................................................................16 4.4.6 Power Control Modes .........................................................................................................................................16 4.5 HOST CONTROLLER.......................................................................................................................................................19 4.5.1 Legacy Support ..................................................................................................................................................20 4.5.2 Intercept Port 60h and 64h Accesses.................................................................................................................20 4.6 GENERAL PURPOSE PINS...............................................................................................................................................21 5.0 REGISTER DESCRIPTIONS .........................................................................................................................................23 5.1 PCICFG REGISTER SPACE ...........................................................................................................................................23 5.1.1 Programming Differences from 82C861 Component..........................................................................................23 5.1.2 PCICFG 00h-FFh ...............................................................................................................................................24 5.2 HOST CONTROLLER REGISTER SPACE ............................................................................................................................29 5.2.1 MEMOFST 00h-5Ch...........................................................................................................................................29 5.2.2 Legacy Support Registers ..................................................................................................................................39 5.2.3 MEMOFST 100h-1Fh (Legacy Support Registers).............................................................................................39 6.0 ELECTRICAL RATINGS................................................................................................................................................41 6.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................41 6.2 DC CHARACTERISTICS: .................................................................................................................................................41 6.3 AC CHARACTERISTICS (PRELIMINARY) ............................................................................................................................42 6.3.1 PCI Bus AC Timings...........................................................................................................................................42 6.3.2 USB AC Timings: Full Speed Source .................................................................................................................43 6.3.3 USB AC Timings: Low Speed Source ................................................................................................................44 7.0 8.0 MECHANICAL PACKAGE OUTLINES .........................................................................................................................46 NAND TREE TEST MODE.............................................................................................................................................47
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* Implements CLKRUN# pin to support hardwareenforced power-down * Packaged as 100-pin LQFP (Low-profile Quad Flat Pack) * Supported by Windows 98, Windows 2000, and Windows CE
1.0
Features
* Compliant with USB rev. 1.1 specification * Fully compatible with USB OHCI specification * Two independent host controllers, two ports each, making FireLink USB a multi-function PCI device * Second host controller can be disabled if not used * Clock input can be derived from either a 12MHz crystal or a 48MHz oscillator * Clocks can be turned off when not in use to save power * Core operates at 3.3V; PCI inputs are 5V-tolerant * Incorporates PCI Power Management, supporting very low power standby modes
2.0
Overview
This document describes the OPTi FireLink USB (82C862) controller. This PCI-to-USB bridge is unique in that it consists of two independent dual-port controllers, each sharing only the common PCI bus connection. This arrangement allows for a total Universal Serial Bus bandwidth of 24Mb/s, divided into 12Mb/s for each pair of ports. Figure 1 provides a block diagram of the overall functionality of the chip.
Figure 1.
82C862 FireLink USB Block Diagram
FireLink USB
82C862
PCI i n terface C e n tr a l Arbiter
port 1
USB C o n tro ller M odule 1 U S B C o n fig R e gs Function 0
port 2
port 3
USB C o n tro ller M odule 2 U S B C o n fig R e gs Function 1
R E Q #, GNT#
port 4
48MHz Clock Generatio n
12M H z xtal
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3.0
3.1
Signal Definitions
Terminology/Nomenclature Conventions
The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used extensively. This is done to avoid confusion when working with a mixture of active low and active high signals. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. The tables in this section use several common abbreviations. Table 1 lists the mnemonics and their meanings. Note that TTL/CMOS/Schmitt-trigger levels pertain to inputs only. Outputs are driven at CMOS levels.
Table 1. Signal Definitions Legend
Mnemonic Analog CMOS Dcdr Diff Ext G I Int I/O Mux NIC O OD P PD PU S S/T/S TTL Description Analog-level compatible CMOS-level compatible Decoder Differential signal pair External Ground Input Internal Input/Output Multiplexer No Internal Connection Output Open drain Power Pull-down resistor Pull-up resistor Schmitt-trigger Sustain Tristate TTL-level compatible
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Figure 2.
Note: LQFP Pin Diagram (Note) Figure 3-1 shows a pin diagram of the 82C862 packaged in an LQFP (Low-profile Quad Flat Pack, square). Refer to Section 6.0, "Mechanical Package Outlines" for details regarding packaging.
AD3 AD4 INTB# SMI# GND AD5 AD6 AD7 VCC PWRFLT4# PWRON4# C/BE0# AD8 AD9 AD10 GND AD11 AD12 AD13 VCC GND AD14 AD15 C/BE1# PAR 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
INTA# AD2 AD1 AD0 GND X1/CLK48 VCC X2 AGND_PLL AVCC_PLL DGND_USB AGND_USB D1+ D1D2+ D2AVCC_USB DVCC_USB RESET# GND TEST0 VCC PWRFLT2# PWRON2# TEST1
FireLink USB
82C862
SERR# PWRFLT3# PWRON3# PME# PERR# STOP# DEVSEL# TRDY# IRDY# GND VCC FRAME# C/BE2# AD16 AD17 VCC GND AD18 AD19 AD20 AD21 PWRFLT1# PWRON1# AD22 AD23
DVCC_USB AVCC_USB D4D4+ D3D3+ AGND_USB DGND_USB PCICLK GNT# REQ# AD31 AD30 AD29 GND VCC AD28 AD27 AD26 AD25 CLKRUN# GND AD24 C/BE3# IDSEL
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3.2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Numerical Pin Cross-Reference List
Signal Name Power Plane Pin No. 35 36 37 38 39 40 41 42 AVCC_PLL DVCC_USB AVCC_USB 43 44 45 46 47 48 49 50 51 DVCC_USB VCC 52 53 54 55 56 57 58 59 DVCC_USB AVCC_USB 60 61 62 63 64 65 66 DVCC_USB VCC 67 68 Signal Name Power Plane Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name Power Plane
INTA# AD2 AD1 AD0 GND X1/CLK48 VCC X2 AGND_PLL AVCC_PLL DGND_USB AGND_USB D1+ D1D2+ D2AVCC_USB DVCC_USB RESET# GND TEST0 VCC PWRFLT2 PWRON2 TEST1 DVCC_USB AVCC_USB D4D4+ D3D3+ AGND_USB DGND_USB PCICLK
VCC
GNT# REQ# AD31 AD30 AD29 GND VCC AD28 AD27 AD26 AD25 CLKRUN# GND AD24 C/BE3# IDSEL AD23 AD22 PWRON1# PWRFLT1# AD21 AD20 AD19 AD18 GND VCC AD17 AD16 C/BE2# FRAME# VCC GND IRDY# TRDY#
VCC
DEVSEL# STOP# PERR# PME# PWRON3# PWRFLT3# SERR# PAR C/BE1# AD15 AD14 GND VCC AD13 AD12 AD11 GND AD10 AD9 AD8 C/BE0# PWRON4# PWRFLT4# VCC AD7 AD6 AD5 GND SMI# INTB# AD4 AD3
VCC
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3.3
3.3.1
Signal Descriptions
Clock and Reset Interface Signals
Pin No. 34 Pin Type I Signal Description PCI Clock: This input provides timing for all cycles on the host PCI bus; normally 33MHz. All other PCI signals are sampled on the rising edge of PCLK (timing parameters refer to this edge). USB Clock: The CLK48 input provides timing for USB data signals; this clock must be 48MHz for proper USB operation. As an option, a 12MHz crystal can be connected across X1 and X2, in which case an internal PLL will develop the 48MHz signal. Refer to the TEST0-TEST1 strap options for selecting the mode of operation. Reset: If RESET# is asserted for a minimum of 1s while PCICLK is stable at 33MHz, it causes the 82C862 to enter its default state (all registers are set to their default values). AD[31:0], C/BE[3:0]#, and PAR are always driven low by the 82C862 synchronously from the leading edge of RESET# and are always tristated from the trailing edge of RESET#. FRAME#, IRDY#, TRDY#, STOP#, and DEVSEL# are tristated from the leading edge of RESET# and remain so until driven as either a master or slave by the 82C862. RESET# may be asynchronous to PCICLK when asserted or negated, however, negation must occur with a clean, bounce-free edge.
Signal Name PCICLK
X1/CLK48 X2
6 8
I O
RESET#
19
O
3.3.2
PCI Bus Interface Signals
Pin No. 37:39, 42:45, 49, 51, 55:58, 61:62, 78:79, 82:84, 86:88, 93:95, 99:100, 2:1 Pin Type I/O Signal Description Address and Data Lines 31 through 0: This bus carries the address and/or data during a PCI bus cycle. A PCI bus cycle has two phases - an address phase which is followed by one or more data phases. During the initial clock of the bus cycle, the AD bus contains a 32-bit physical byte address. AD[7:0] is the least significant byte (LSB) and AD[31:24] is the most significant byte (MBS). After the first clock of the cycle, the AD bus contains data. When the 82C862 is the target, AD[31:0] are inputs during the address phase. For the data phase(s) that follow, the 82C862 may supply data on AD[31:0] in the case of a read or accept data in the case of a write. When the 82C862 is the master, it drives a valid address on AD[31:2] during the address phase, and drives write or accepts read data on AD[31:0] during the data phase. As a master, the 82C862 always drives AD[1:0] low. I/O Bus Command and Byte Enables 3 through 0: These signals provide the command type information during the address phase and carry the byte enable information during the data phase. C/BE0# corresponds to byte 0, C/BE1# to byte 1, C/BE2# to byte 2, and C/BE3# to byte 3. If the 82C862 is the initiator of a PCI bus cycle, it drives C/BE[3:0]#. When it is the target, it samples C/BE[3:0]#.
Signal Name AD[31:0]
C/BE[3:0]#
49, 63, 77, 89
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PAR 76 O Even Parity: The 82C862 calculates PAR for both the address and data phases of PCI cycles. PAR is valid one PCI clock after the associated address or data phase, but may or may not be valid for subsequent clocks. It is calculated based on 36 bits - AD[31:0] plus C/BE[3:0]#. "Even" parity means that the sum of the 36 bit values plus PAR is always an even number, even if one or more bits of C/BE[3:0]# indicate invalid data. Cycle Frame: This signal is driven by the current PCI bus master to indicate the beginning and duration of an access. The master asserts FRAME# at the beginning of a bus cycle, sustains the assertion during data transfers, and then negates FRAME# in the final data phase. FRAME# is an input when the 82C862 is the target and an output when it is the initiator. FRAME# is tristated from the leading edge of RESET# and remains tristated until driven as either a master or slave by the 82C862. IRDY# 67 I/O (s/t/s) Initiator Ready: IRDY#, along with TRDY#, indicates whether the 82C862 is able to complete the current data phase of the cycle. IRDY# and TRDY# are both asserted when a data phase is completed. During a write, the 82C862 asserts IRDY# to indicate that it has valid data on AD[31:0]. During a read, the 82C862 asserts IRDY# to indicate that it is prepared to accept data. IRDY# is an input when the 82C862 is a target and an output when it is the initiator. IRDY# is tristated from the leading edge of RESET# and remains tristated until driven as either a master or a slave by the 82C862. TRDY# 68 I/O (s/t/s) Target Ready: TRDY#, along with IRDY#, indicates whether the 82C862 is able to complete the current data phase of the cycle. TRDY# and IRDY# are both asserted when a data phase is completed. When the 82C862 is acting as the target during read and write cycles, it performs in the following manner: 1. During a read, the 82C862 asserts TRDY# to indicate that it has placed valid data on AD[31:0]. 2. During a write, the 82C862 asserts TRDY# to indicate that is prepared to accept data. TRDY# is an input when the 82C862 is the initiator and an output when it is the target. TRDY# is tristated from the leading edge of RESET# and remains so until driven as either a master or a slave by the 82C862. STOP# 70 I/O (s/t/s) Stop: STOP# is an output when the 82C862 is the target and an input when it is the initiator. As the target, the 82C862 asserts STOP# to request that the master stop the current cycle. As the master, the assertion of STOP# by a target forces the 82C862 to stop the current cycle. STOP# is tristated from the leading edge of RESET# and remains so until driven by the 82C862 acting as a slave.
FRAME#
64
I/O (s/t/s)
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DEVSEL# 69 I/O (s/t/s) Device Select: The 82C862 claims a PCI cycle via positive decoding by asserting DEVSEL#. As an output, the 82C862 drives DEVSEL# for two different reasons: 1. If the 82C862 samples IDSEL active in configuration cycles, DEVSEL# is asserted. 2. When the 82C862 decodes an internal address or when it subtractively decodes a cycle, DEVSEL# is asserted When DEVSEL# is an input, it indicates the target response to an 82C862 master-initiated cycle. DEVSEL# is tristated from the leading edge of RESET# and remains so until driven by the 82C862 acting as a slave. IDSEL 50 I Initialization Device Select: This signal is the "chip select" during configuration read and write cycles. IDSEL is sampled by the 82C862 during the address phase of a cycle. If IDSEL is found to be active and the bus command is a configuration read or write, the 82C862 claims the cycle with DEVSEL#. Parity Error: The 82C862 uses this line to report data parity errors during any PCI cycle except a Special Cycle. System Error: The 82C862 uses this line to report address parity errors and data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Bus Request: REQ# is asserted by the 82C862 to request ownership of the PCI bus. Bus Grant: GNT# is sampled by the 82C862 for an active low assertion, which indicates that it has been granted use of the PCI bus. Clock Run: The CLKRUN# function is available on this pin and can be used to reduce chip power consumption during idle periods. It is an I/O sustained tristate signal and follows the PCI 2.1 defined protocol. General Purpose I/O pin 2: These pins can be written or read by specific application software. Refer to PCICFG 53-55h for information.
PERR# SERR#
71 75
I/O I
REQ# GNT# CLKRUN#
36 35 46
O I I/O
GPIO2
3.3.3
USB Interface Signals
Pin No. 13/14 15/16 28/29 30/31 53 24 73 90 54 23 74 91 Pin Type diff diff diff diff O Signal Description USB Port 1 Differential Data Pair: This pair comes from the first controller. USB Port 2 Differential Data Pair: This pair comes from the first controller. USB Port 3 Differential Data Pair: This pair comes from the second controller. USB Port 4 Differential Data Pair: This pair comes from the second controller. Power On Lines 1, 2, 3 and 4: These outputs are used to switch port VCC for the respective USB port. The controlled VCC is used only by the device connected to the port, and is not used by the 82C862 controller. Power Fault Lines 1, 2, 3 and 4: These inputs indicate that an over-current fault has occurred on the respective USB port. Their polarity can be both strap- and software-controlled: Refer to the Strap Options section for details.
Signal Name D1+/D1D2+/D2D3+/D3D4+/D4PWRON1# PWRON2# PWRON3# PWRON4# PWRFLT1# PWRFLT2# PWRFLT3# PWRFLT4#
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3.3.4 Host Controller shared signals: PME#, SMI#, REQ#, GNT#
Several other signals are shared by both host controllers in addition to the bused PCI signals. The shared signals are all active low. The diagram below best explains the internal connections of the 82C862 device.
FireLink USB USB Host1 GNT1# REQ1# SMI1# PME1# Internal Arbiter GNT# REQ#
USB Host2
GNT2# REQ2# SMI2# PME2# PME# SMI#
3.3.5
Legacy and Interrupt Interface Signals
Pin No. 97 Pin Type O Signal Description System Management Interrupt: This signal is used to request a System Management Mode (SMM) interrupt. It can be connected to a spare EPMI pin on the host chipset. General Purpose I/O pin 4: These pins can be written or read by specific application software. Refer to PCICFG 53-55h for information. 72 special Power Management Event: This signal is used to wake up the system from a PCI Power Management (PCI/PM) power saving mode. This pin is normally tristated and is driven low when active. Note: When unpowered, the PME# driver output circuit will not be damaged if PME# is powered from another source. Moreover, once power is removed from the chip, this pin does not present a current path to ground.
Signal Name SMI#
GPIO4 PME#
GPIO3 INTA# TEST0 GPIO0 TEST1 GPIO1 25 I/O 1 21 O I/O
General Purpose I/O pin 3: These pins can be written or read by specific application software. Refer to PCICFG 53-55h for information. PCI Interrupt A: This signal can be connected to a PCI interrupt line. TEST Pin 0: This pin is sampled by the chip at reset time to put the logic into a test mode if needed. See the STRAP OPTIONS section for details. General Purpose I/O pin 0: These pins can be written or read by specific application software. Refer to PCICFG 53-55h for information. TEST Pin 1: This pin is sampled by the chip at reset time to put the logic into a test mode if needed. See the STRAP OPTIONS section for details. General Purpose I/O pin 1: These pins can be written or read by specific application software. Refer to PCICFG 53-55h for information.
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3.3.6 Power and Ground Pins
Pin No. 7, 22, 41, 60, 65, 81, 92, 10 17, 27 18, 26 20,40,47, 59,66,80, 85,96 9 12, 32 11, 33 Pin Type P Signal Description 3.3V Power Connection: Core voltage is always 3.3V. However, the PCI interface can be 5V as the PCI inputs are 5V-tolerant. PLL Analog Power: Connect to low-noise 3.3V. USB I/O Analog Power: Connect to low-noise 3.3V. USB I/O Digital Power: Connect to 3.3V. Core Digital Ground: Connect to board ground. Signal Name VCC
AVCC_PLL AVCC_USB DVCC_USB GND
P P P G
AGND_PLL AGND_USB DGND_USB
G G G
PLL Analog Ground: Connect to same board ground as GND. USB I/O Analog Ground: Connect to same board ground as GND. USB I/O Digital Ground: Connect to same board ground as GND.
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3.3.7 Strap Options
The 82C862 component offers several operating mode choices at power-up time. These choices are selected through a strap resistor that pulls the related pin either up or down to the required level. A 4.7k ohm resistor is recommended.
Table 2. Strap Selected Options
Pin
PWRON3# 1 0 TEST0 0 0 1 1 SMI# 0 1 PWRON2# 1 TEST1 0 1 1 0 Enable/Disable Second Host Enable Second USB Host Controller (Function 1) [DEFAULT] Disable Second USB Host Controller. All clocks going to the logic for the second host are stopped to reduce power consumption. Mode Operation PLL Operational Mode using 12 MHz crystal on X1 and X2 [DEFAULT] 48 MHz clock Operation Mode. X1 connects to 48 MHz clock, X2 no-connect. NAND Tree test mode Tristate test mode PCI Power Management PME# function / Reference USB clock PME# becomes 48 MHz reference clock output from PLL. Used for testing PLL. Also disables PCI power management, PCICFG 06h[4] = 0. Enables PME# function and PCI power management, PCICFG 06h[4]=1. [DEFAULT] Global/Individual Power Control Individual PWRON# and PWRFLT# for each port: [DEFAULT] HcRhDescA NoPowerSwitching=0 (MEMOFST 49h[1]) HcRhDescA PowerSwitchingMode=1 (MEMOFST 49h[0]) HcRhDescB PortPowerControlMask bit1,bit2=1,1 (MEMOFST4Eh[1,2]) HcRhDescA NoOvercurrentProtection=0 (MEMOFST 49h[4]) HcRhDescA OvercurrentProtectionMode=1 (MEMOFST 49h[3]]) Global PWRON# and PWRFLT# for each port: HcRhDescA NoPowerSwitching=0 (MEMOFST 49h[1]) HcRhDescA PowerSwitchingMode=0 (MEMOFST 49h[0]) HcRhDescB PortPowerControlMask bit1,bit2=0,0 (MEMOFST4Eh[1,2]) HcRhDescA NoOvercurrentProtection=0 (MEMOFST 49h[4]) HcRhDescA OvercurrentProtectionMode=0 (MEMOFST 49h[3]])
Mode
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4.0
4.1
Functional Description
Universal Serial Bus (USB)
The 82C862 controller supports a PCI-based implementation of Universal Serial Bus utilizing the OpenHCI core developed by Compaq. The logic core consists of two USB host controller modules (making the 82C862 part a multi-function PCI device), and a PCI interface controller. Each USB host controller module contains an integrated root hub that supports two downstream USB hubs or devices. Keyboard and mouse legacy support are also included for DOS compatibility with USB devices. This legacy support operates in conjunction with the primary host controller module as described later in this document. This document must be used along with the following public domain reference documents to get the complete functional description of the USB core implementation.
* * *
USB Specification, Revision 1.1 OpenHCI Specification, Revision 1.0a PCI Specification, Version 2.1
A functional block diagram of one of the two USB controller modules is given in Figure 4-1. The other is identical. Figure 4-1 CLKRUN# PCI Bus USB Functional Block Diagram
PCI Interface I2C Interface PCI Master Core Clock Control Logic PCI Slave PCI Config I2CCLK I2CDATA Serial ROM SODIMM
PCI I/O
KBD Legacy
List Processor Bus Master
Frame Management Port 1
PWRGD1 PWRFLT1 PWRON1 VD1+ VD1-
USB 1
Clock Gen Data Buffer Engine
Global Operation s Root Hub Control USB SIE Port 2
PWRGD2 PWRFLT2 PWRON2 VD2+ VD2-
USB 2
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4.2 PCI Controller
The PCI controller interfaces the host controller to the PCI bus. As a master, the PCI controller is responsible for running cycles on the PCI bus on behalf of the host controller. As a target, the PCI controller monitors the cycles on the PCI bus and determines when to respond to these cycles. A USB host controller module is a PCI target when it decodes cycles to its internal PCI configuration registers or to its internal PCI memory mapped I/O registers. The PCI controller asserts DEVSEL# in medium decode timing to claim a PCI transaction. Since two PCI-interfaced USB controller modules reside on-chip, the logic includes an internal arbiter to select between the two modules when one or both make a bus mastering request. The PCI configuration space of the primary USB host controller module is accessed as Device #X, Function #0, where Device #X depends on which AD line is connected to the IDSEL input. For the secondary USB host controller module, PCI configuration register space is accessed as Function #1 instead. PCI configuration space is hereafter referred to as PCICFG. Table 3 gives a register map of the PCICFG register space (duplicated for each of the two functions). Refer to Section 5.1, "PCICFG Register Space" for detailed bit information.
Table 3. PCI Controller Register Map
PCICFG 00h-01h 02h-03h 04h-05h 06h-07h 08h 09h-0Bh 0Ch 0Dh 0Eh 0Fh 10h-13h 14h-2Bh 2Ch-2Dh 2Eh-2Fh 30h-3Bh 3Ch 3Dh 3Eh R/W RO RO R/W R/W RO RO R/W R/W RO -R/W -RO RO -R/W R/W R/W Register Name Vendor ID Device ID Command Status Revision ID Class Code Cache Line Size Master Latency Timer Header Type Reserved Base Address Register 0 Reserved Subsystem Vendor Subsystem ID Reserved Interrupt Line Interrupt Pin Minimum Grant PCICFG 3Fh 40h-45h 46h-4Bh 4Ch 4Dh 4Eh-4Fh 50h 51h 52h 53h 54h 55h 56h-7Bh 7Ch-7Fh 80h-EFh F0h-F5h F6h-FFh R/W R/W --R/W R/W -R/W -R/W R/W R/W R/W -R/W -R/W -Register Name Maximum Latency Reserved for factory test Reserved Interrupt Pin Selection Miscellaneous Control Reserved PCI Host Feature Control Reserved Strap Option Override GPIO Select GPIO Output Enable GPIO Data Reserved Subsystem ID Restore Reserved PCI Power Management Reserved
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4.3 Clock Generation
The USB core requires an accurate 48MHz internal clock for proper operation. This clock can be obtained either by connecting an external 48MHz oscillator, or by connecting a 12MHz crystal. To use the external 48MHz clock, connect the clock source to the X1 pin and strap TEST1 high. The X2 pin is not used in this configuration and must be left floating. This clock must be accurate to +/- 0.2%, or 2000ppm. To use a 12MHz crystal, connect it to the X1 and X2 pins and strap TEST1 low. An internal PLL develops the required 48MHz clock. This PLL can be powered down when not in use through the PCI Power Management registers. Since the 12MHz clock generated is used to develop 48MHz internally, its accuracy must be within +/- 0.05%, or 500ppm.
4.4
Power Management Features
FireLink USB 82C862 implements new power management features which can reduce the overall power consumed in mobile USB applications. Key features are as follows. The OS can put each USB controller module individually into USBSuspend state. Once in USBSuspend state, the BIOS can turn off the USB I/O cells on each port for further power savings. The external PCI clock can be stopped if system hardware is designed to use the CLKRUN# pin from the 82C862 chip, which can also be used to awaken the system. The external 48MHz USB clock can also be stopped along with the PCICLK when the system will be put into a Standby mode. USB clocks to each of the internal modules can be stopped independently through the PCI power management registers. Each of these features is described in the sections below.
4.4.1
Putting FireLink into USBSuspend State
Before a host system goes into a suspend state, the operating system should put the OHCI USB controller into USBSuspend mode by writing to register MEMOFST 04h[7:6] = 11.
4.4.2
Powering Down the USB I/O Cells
Once in USBSuspend state, the USB I/O cells can be disabled to reduce power by setting PCICFG 50h[1:0] = 11. If this feature is used, the I/O cells should be disabled by the BIOS before going into system-level Suspend, and re-enabled by the BIOS before giving control back to the operating system.
4.4.3
Stopping the 48MHz USB Clock
After the controller is put into USBSuspend state, still another step can be taken to further reduce power consumption: stop the 48MHz USB clock. If this route is taken, the USB clock must be stopped and started in a glitch free manner. The usual means of effecting this control would be through software control of the system clock generator circuit. Once the USB clock is stopped, the system can be awakened by using PME#, which will be asserted on a USB wake up event (resume signalling, connect, disconnect). This system event should be designed to restart the 48MHz clock to the USB controller.
4.4.4
Using CLKRUN#
The CLKRUN# pin is always operational in the 82C862 part; no enabling is required. The PCI Mobile Design Guide, available from the PCISIG, describes the operation of CLKRUN# in detail. Briefly, connected devices monitor this pin to see if it goes high, indicating that the host wants to stop the system PCICLKs. If the line goes high, connected devices are allowed to momentarily drive the pin low. The host will then take over driving this pin low until it wants to try again to stop the clocks. The host system uses CLKRUN# to determine whether or not the 82C862 USB controller requires a PCI clock by releasing CLKRUN#, which is always pulled high with a resistor. The USB controller power management logic will drive this pin low again as required by the CLKRUN# specification if the controller is using the clock, i.e. whenever a USB device is attached. If the controller does not drive the clock low, the system is free to slow or stop the PCI clock.
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4.4.5 Stopping the Internal USB Clocks
The 82C862 device is equipped with PCI Power Management registers. When either function is set to D3hot mode, its internal USB clock is switched off to effect a significant reduction in power consumption. Returning the system to D0 will restart the internal USB clock.
4.4.6
Power Control Modes
The 82C862 pinout includes the following signals for controlling and monitoring USB power for the respective USB port: * PWRON1-4# are active-low outputs to turn USB power on. * PWRFLT1-4# are active-low inputs to detect over current. At design time, it must be decided whether these control and monitoring signals will be used independently on a per-port basis (ideal situation), or paired together (for lower component cost). Consequently, the chip can strap into one of two power control modes: * Individual PWRON# and PWRFLT# - entered when PWRON2# is sensed high at reset * Global PWRON# and PWRFLT# - entered when PWRON2# is sensed low at reset. The 82C862 part supports two modes for turning on power to the respective USB ports: Global and Individual (per-port). This logic is contained in the Root Hub partition of each USB controller module, and consists of a portion for the Root Hub itself as well as portions for each individual port. The operation of Global and Individual power switching is explained below. Global Power Switching is the mode that is supported in the original 82C861 design. In this mode either PWRON1# or PWRON2# can be used to turn on power for both ports on USB Host 1, and either PWRON3# or PWRON4# can be used to turn on power for both ports USB Host 2. When supporting this mode the following registers are of significance:
Register HcRhDescriptorA HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhStatus
Field NoPowerSwitching MEMOFST 49h[1] PowerSwitchingMode MEMOFST 49h[0] PortPowerControlMask MEMOFST 4Eh[2:1] ClearGlobalPower (write) MEMOFST 50h[0] SetGlobalPower (write) MEMOFST 52h[0] PortPowerStatus (read) MEMOFST 55h[0] port 1 MEMOFST 59h[0] port 2
Value or Function 0: Ports are power switched 0: All ports are powered at the same time Not Used This bit is written to `1' to turn OFF power to all ports. This bit is written to `1' to turn ON power to all ports. 0=port power is off 1=port power is on Only Set/ClearGlobalPower controls this bit
HcRhPort1Status HcRhPort2Status
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Individual Power Switching is the mode in which the power to the USB ports can be controlled individually by using the Port Status registers for each port, or can also be controlled globally depending on the value in the PowerControlMask register. When strapping into this mode, the PowerControlMask registers will be set. All four signals, PWRON1#, PWRON2#, PWRON3#, and PWRON4# will be used to turn on the respective USB ports power and will be independently controlled. When supporting this mode the following registers are of significance:
Register HcRhDescriptorA HcRhDescriptorA Field NoPowerSwitching MEMOFST 49h[1] PowerSwitchingMode MEMOFST 49h[0] PortPowerControlMask MEMOFST 4Eh[2:1] Value or Function 0: Ports are power switched 1: Each port is powered individually. This mode allows the port to be either global or individual controlled depending on value in PortPowerControlMask. This register determines if the ports power is controlled individually by the Port Status register, or globally by the Root Hub Status register. 0=port uses global Set/ClearGlobalPower 1=port uses per-port Set/ClearPortPower This bit is written to `1' to turn off power to ports whose PortPowerControlMask=0. This bit is written to `1' to turn on power to ports whose PortPowerControlMask=0. 0=port power is off 1=port power is on If per-port switching is enabled for this port, then only Set/ClearPortPower affect this bit. If global mode is enabled, then Set/ClearGlobalPower control this bit. 1: sets PortPowerStatus Only valid if port is enabled for per-port switching. 1: clear PortPowerStatus Only valid if port is enabled for per-port switching.
HcRhDescriptorB
HcRhStatus HcRhStatus
ClearGlobalPower (write) MEMOFST 50h[0] SetGlobalPower (write) MEMOFST 52h[0] PortPowerStatus (read) MEMOFST 55h[0] port 1 MEMOFST 59h[0] port 2
HcRhPort1Status HcRhPort2Status
HcRhPort1Status HcRhPort2Status HcRhPort1Status HcRhPort2Status
SetPortPower (write) MEMOFST 55h[0] port 1 MEMOFST 59h[0] port 2 ClearPortPower (write) MEMOFST 55h[1] port 1 MEMOFST 59h[1] port 2
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The 82C862 logic also supports both Global and per-port overcurrent detection as follows. Global overcurrent mode - either PWRFLT1# or PWRFLT2# can be used to detect an overcurrent condition on any port on USB Host 1, and either PWRFLT3# or PWRFLT4# can be used to detect an overcurrent condition on any port on USB Host 2. For example, if PWRFLT1# is asserted, it means an overcurrent condition exists on USB Host 1, resulting in power shutoff for both ports on USB Host 1, and setting of the appropriate global overcurrent indicator bits.
Register HcRhDescriptorA HcRhDescriptorA HcRhStatus HcRhStatus Field NoOvercurrentProtection MEMOFST 49h[4] OverCurrentProtectionMode MEMOFST 49h[3] OverCurrentIndicator MEMOFST 50h[1] OverCurrentIndicatorChange MEMOFST 52h[1] PortOverCurrentIndicator MEMOFST 54h[3] port 1 MEMOFST 58h[3] port 2 PortOverCurrentIndicatorChange MEMOFST 56h[3] port 1 MEMOFST 5Ah[3] port 2 Value or Function 0: Over-current status is reported 0: Global - Over-current reported collectively for all ports 1: Global over-current exists 0: power operations normal Set by hardware when OverCurrentIndicator bit changes. Write a `1' to clear this bit. Not used, set to `0' for global overcurrent. Not used, set to `0' for global overcurrent.
HcRhPort1Status HcRhPort2Status HcRhPort1Status HcRhPort2Status
Per-Port overcurrent mode - PWRFLT1 #, PWRFLT2#, PWRFLT3#, and PWRFLT4# are all used to monitor each port individually. If an overcurrent condition exists on one port, power is only shut off to that port.
Register HcRhDescriptorA HcRhDescriptorA HcRhStatus HcRhStatus Field NoOvercurrentProtection MEMOFST 49h[4] OverCurrentProtectionMode MEMOFST 49h[3] OverCurrentIndicator MEMOFST 50h[1] OverCurrentIndicatorChange MEMOFST 52h[1] PortOverCurrentIndicator MEMOFST 54h[3] port 1 MEMOFST 58h[3] port 2 PortOverCurrentIndicatorChange MEMOFST 56h[3] port 1 MEMOFST 5Ah[3] port 2 Value or Function 0: Over-current status is reported 1: Over-current is reported on a perport basis Not used, always `0' for per-port over-current mode. Not used, always `0' for per-port over-current mode. 0: no over-current condition 1: over-current condition exists Set by hardware when PortOverCurrentIndicator bit changes. Write a `1' to clear this bit.
HcRhPort1Status HcRhPort2Status HcRhPort1Status HcRhPort2Status
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4.5 Host Controller
This block is the operational control block in the USB core. It is responsible for the host controller operational states (Suspend, Disabled, Enabled), special USB signaling (Reset, Resume), status, interrupt control, and host controller configuration information. The host controller (HC) interface registers are PCI memory mapped I/O, hereafter referred to as MEMOFST. Table 4-2 gives a register map for the MEMOFST register space. Refer to Section 5.2, "Host Controller Register Space" for detailed bit information.
Table 4. Host Controller Register Map
MEMOFST 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-3Fh 40h-43h 44h-47h 48h-4Bh 4Ch-4Fh 50h-53h 54h-57h 58h-5Bh R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterrupt Enable HcInterrupt Disable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPort1Status HcRhPort2Status
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4.5.1 Legacy Support
Four registers are provided for legacy support: 1. HceControl - - Used to enable and control the emulation hardware and report various status information. 2. HceInput - - Emulation side of the legacy Input Buffer register. 3. HceOutput - - Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software. 4. HceStatus - - Emulation side of the legacy Status register. These registers are located in the Host Controller Register Space; from MEMOFST 100h through 10Fh. Table 4-3 shows a register map of these registers. Refer to Section 5.2.2, "Legacy Support Registers" for detailed bit information.
Table 5. Legacy Support Register Map
MEMOFST 100h-103h 104h-107h 108h-10Bh 10Ch-10Fh R/W R/W R/W R/W R/W Register Name HceControl HceInput HceOutput HceStatus
4.5.2
Intercept Port 60h and 64h Accesses
The HceStatus, HceInput, and HceOutput registers are accessible at I/O Ports 60h and 64h when emulation is enabled. Reads and writes to these registers using the I/O Ports do have some side effects as shown in Table 4-4. However, accessing these registers directly through their memory address produces no side effects. When emulation is enabled, I/O accesses of Ports 60h and 64h must be handled by the Host Controller (HC). The HC must be positioned in the system so that it can do a positive decode of accesses to Ports 60h and 64h on the PCI bus. If a keyboard controller is present in the system, it must either use subtractive decode or have provisions to disable its decode of Ports 60h and 64h. If the legacy keyboard controller uses positive decode and is turned off during emulation, it must be possible for the emulation code to quickly re-enable and disable the legacy keyboard controller Port 60h and 64h decode. This is necessary to support a mixed operating environment.
Table 6. Emulated Registers and Side Effects
Register Contents Accessed/Modified HceOutput HceInput Side Effect * A read from Port 60h will set the Output Full bit (MEMOFST 10Ch[0]) to 0. * A write to Port 60h will set the Input Full bit (MEMOFST 10Ch[1]) to 1 and the Cmd Data bit (MEMOFST 10Ch[3]) to 0. * A write to Port 64h will set the: Input Full bit (MEMOFST 10Ch[1]) to 0 and the Cmd Data bit (MEMOFST 10Ch[3]) to 1. HceStatus * A read from Port 64h returns the current value of the HceStatus register.
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4.6 General Purpose Pins
The strap pins TEST0, TEST1, CLKRUN#, PME#, and SMI# are multifunction pins that offer general purpose I/O (GPIO) functionality. At reset time these pins are always input pins. After being sampled at reset to determine strap selections for the chip logic, these pins can be programmatically selected to be GPIO signals. TEST0 and TEST1 are automatically available as GPIO pins after reset is de-asserted, since they have no other assigned functions. The other pins must be specifically enabled for GPIO if their primary function assignment is not needed. The PIO mapping is as follows.
Signal TEST0 TEST1 CLKRUN# PME# SMI#
PIO signal mapped to PIO0 PIO1 PIO2 PIO3 PIO4
Refer to PCICFG 53h, 54h, and 55h for information on selection and direction of PIO pins. Note that PIO pins can be used along with host CPU software to generate I2C interface signaling; contact OPTi for details or sample code.
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5.0
Register Descriptions
The 82C862 has three types of register spaces: 1. PCI Configuration Register Space 2. Host Controller Register Space 3. I/O Register Space The subsections that follow detail the locations and access mechanisms for the registers located within these register spaces. Notes: 1. All bits/registers are read/write and their default value is 0 unless otherwise specified. 2. All reserved bits/registers MUST be written to 0 unless otherwise specified.
5.1
PCICFG Register Space
The FireLink USB 82C862 part is a multi-function PCI device. Function 0: Primary USB host controller module Function 1: Secondary USB host controller module. The two USB controller modules each have their own PCI configuration space. The configuration space of both USB controllers are similar except for the value in the Interrupt Pin register (PCICFG 3Dh) and the Interrupt Pin Selection register (PCICFG 4Ch), because the controllers are assigned different interrupt pins by default. The configuration space of each PCI USB controller module is referred to as PCICFG. The bit formats for these registers are described in Section 5.1.2.
5.1.1
Programming Differences from 82C861 Component
While the physical device part number of this chip is 82C862, the USB controller modules identify themselves as 82C861 to maintain backward software compatibility with the previous OPTi chip. Software can differentiate between the chips by reading the Revision ID of 20h in PCICFG 08h (previous revisions read back 10h or lower). Additional revision 20h changes that relate to the programming interface are as follows. * The 82C862 component adds PCI power management, reflected in changes in PCICFG 06h and the addition of PCICFG 34h, 4Dh, and F0-F5h. * The 82C862 part provides a way to restore the Subsystem Vendor ID and Subsystem ID values in a single-step process, necessary for proper context restoration after the chip is powered down during OS Suspend operations. This new approach is reflected in the deletion of PCICFG 50h[3] and the addition of PCICFG 7C-7Fh. * The specific I2C pins of the 82C861 part have been replaced by general purpose I/O pins, resulting in the deletion of PCICFG 4Eh. * The IRQ Driveback feature is no longer supported, resulting in the deletion of PCICFG 51h and 54-57h. * Changes to the chip pinout result in major changes to the PCICFG 52h bit definitions. * PCICFG 4Ch has been added to allow both USB controller modules to share a single PCI interrupt. * All bits of MEMOFST 4Bh are now read/writeable (previous chip versions allowed only bits [1:0] to be written).
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5.1.2
7 PCICFG 00h PCICFG 01h PCICFG 02h PCICFG 03h PCICFG 04h Wait cycle control: USB core does not need to insert a wait state between address and data on the AD lines. This bit is always 0. PERR# (response) detection enable bit: 0 = PERR# not asserted 1 = USB core can assert PERR# if it is the receiving data agent and detects a data parity error. VGA palette snooping: This bit is always 0.
PCICFG 00h-FFh
6 5 4 3 2 1 0 Default = 45h Default = 10h Default = 61h Default = C8h Default = 00h USB core can run PCI master cycles: 0 = Disable 1 = Enable USB core responds as a target to memory cycles. 0 = Disable 1 = Enable USB core responds as a target to I/O cycles: 0 = Disable 1 = Enable
Vendor Identification Register (RO)
Device Identification Register (RO)
Command Register - Byte 0 Postable memory write command: Not used when USB core is a master. This bit is always 0. Special Cycles: USB core does not run Special Cycles on PCI. This bit is always 0.
PCICFG 05h
Command Register - Byte 1 Reserved: These bits are always 0. Back-to-back enable: USB core only acts as a master to a single device, so this functionality is not needed. This bit is always 0.
Default = 00h SERR# (response) detection enable bit: 0 = SERR# not asserted 1 = USB core asserts SERR#
PCICFG 06h Fast back-toback capability: USB core supports fast back-to-back transactions when they are not to same agent. This bit is always 1. Reserved
Status Register - Byte 0 Capabilities bit (RO): 0=No PCI Power Management 1=PCI Power Management Available See note. Reserved
Default = 90h
Note: Bit [4] enables extended PCI capabilities. This bit =1 by default, enabling PCI power management capabilities. PCI power management is enabled/disabled by a strap option, which can be overridden by writing PCICFG 4Dh[1]=0 to disable PCI PM, or writing PCICFG 4Dh[1]=1 to enable PCI PM.
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7 PCICFG 07h Detected parity error: SERR# status: Received master abort status: 6 5 4 3 2 1 0 Default = 02h DEVSEL timing (RO): Data parity reported: Set to 1 if PCICFG 04h[6] is set and the USB core detects PERR# asserted while acting as PCI master (whether PERR# was driven by USB core or not.) Default = 20h Default = 10h Default = 03h Default = 0Ch Default = 00h Default = 00h Default = 00h Default = 00h Default = 00h Status Register - Byte 1 Received target abort status: Signaled target abort status:
Indicates DEVSEL# timing when This bit is set to This bit is set to This bit is set to performing a positive decode. 1 whenever the 1 whenever the Set to 1 when This bit is set to 1 when the Since DEVSEL# is asserted to USB core USB core the USB core, 1 when a USB USB core meet the medium timing, these bits are encoded as 01. detects a parity detects a PCI acting as a PCI core generated signals target error, even if address parity master, aborts PCI cycle (USB abort. PCICFG 04h[6] error. a PCI bus core is the PCI Write 1 to clear. is disabled. memory cycle. master) is Write 1 to clear. Write 1 to clear. Write 1 to clear. aborted by a PCI target. Write 1 to clear.
PCICFG 08h PCICFG 09h PCICFG 0Ah PCICFG 0Bh PCICFG 0Ch PCICFG 0Dh PCICFG 0Eh PCICFG 0Fh PCICFG 10h-13h
Revision Identification Register (RO) Class Code Register (RO)
Cache Line Size Register Master Latency Timer Register Header Type Register (RO) Reserved Base Address Register 0
This register identifies the base address of a contiguous memory space in main memory. POST will write all 1s to this register, then read back the value to determine how big of a memory space is requested. After allocating the requested memory, POST will write the upper bytes with the base address. Bits [31:0] correspond to: 10h = [7:0], 11h = [15:8], 12h = [23:16], 13h = [31:24]. - Bit [0] - Indicates that the operational registers are mapped into memory space. Always = 0. - Bits [2:1] - Indicates that the base register is 32 bits wide and can be placed anywhere in 32-bit memory space. Always = 0. - Bit [3] - Indicates no support for prefetchable memory. Always = 0. - Bits [11:4] - Indicates a 4K byte address range is requested, Always = 0. - Bits [31:12] - Base Address: Post writes the value of the memory base address to this register. PCICFG 14h-2Bh PCICFG 2Ch Reserved Subsystem Vendor ID Register (RO) - Byte 0 Default = 00h Default = 45h
The Subsystem Vendor ID register is read-only but its value can be changed through PCICFG 7Dh:7Ch. PCICFG 2Dh PCICFG 2Eh Subsystem Vendor ID Register (RO) - Byte 1 Subsystem ID Register (RO) Byte 0 Default = 10h Default = 61h
The Subsystem ID register is read-only but its value can be changed through PCICFG 7Fh:7Eh. PCICFG 2Fh PCICFG 30h-33h Subsystem ID Register (RO) Byte 1 Reserved Default = C8h Default = 00h
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7 PCICFG 34h 6 5 4 3 2 1 0 Default = F0h Capabilities Pointer Register (RO)
This register provides the offset into the PCI Configuration Space of the USB controller for the location of the PCI Power Management register block. This location is PCICFG F0h PCICFG 35h-3Bh PCICFG 3Ch Reserved Interrupt Line Register Default = 00h Default = 00h
This register identifies the system interrupt controller line to which the interrupt pin of this USB controller module is connected. The value of this register is used by device drivers and has no direct meaning to the USB core. PCICFG 3Dh Interrupt Pin Register Primary Default = 01h Secondary Default = 02h
This register identifies the interrupt pin a device uses. The primary USB controller module uses INTA#, so this value reads 01h by default; the secondary USB controller module uses INTB#, so this value reads 02h by default. The interrupt pin used by each USB controller module can be changed via the respective PCICFG 4Ch[1:0]. PCICFG 3Eh Minimum Grant Register (RO) Reserved PCICFG 3Fh Maximum Latency Register (RO) Reserved PCICFG 40h-44h Reserved These registers are for internal testing purposes. Do not write to these registers. PCICFG 45h Reserved Reserved This register is for internal testing purposes. Do not write to this register. Reserved SIE Pipelining 0=Enable 1=Disable Default = 00h Function 0 Default = 00h Function 1 Default = 01h USB controller interrupt pin: 00 = PCIRQ0# (INTA#) 01 = PCIRQ1# (INTB#) 10 = PCIRQ2# (INTC#) 11 = PCIRQ3# (INTD#) The interrupt pin selected will be reflected in PCICFG 3Dh. PCICFG 4Dh Miscellaneous Control Register Reserved State of Capabilities bit: 0 = Force PCICFG 06h[4] = 0 1 = Force PCICFG 06h[4] = 1 PCICFG 4E-4Fh Reserved Default = 00h Default = 00h Reserved Default = 00h Default = 00h Default = 00h Default = 00h
PCICFG 46h-4Bh PCICFG 4Ch
Reserved Interrupt Pin Selection Register Reserved
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7 PCICFG 50h Reserved 6 5 4 3 2 1 0 Default = 00h Port 2 output: 0 = Enable 1 = Disable Port 1 output: 0 = Enable 1 = Disable PCI Host Feature Control Register Reserved, formerly CLKRUN# mode control Reserved, formerly Subsystem Vendor ID write enable control Reserved, formerly CLKRUN# enable control
(Controls USB (Controls USB I/O cells to save I/O cells to save power) power) Default = 00h Default = 03h SMI# Strap Selection PWRFLT Polarity: PWRON polarity: 0 = High 1 = Low
PCICFG 51h PCICFG 52h Reserved Read/write factory test mode 0=Disable 1=Enable TEST0 Strap Value (RO) 0 = Low 1 = High
Reserved Strap Option Override TEST1 Strap Value (RO) 0 = Low 1 = High PWRON3# Strap Value - Secondary Controller Mode 0 = Disable 1 = Enable
0 = PME# used 0 = High 1 = Low as 48MHz output 1 = PME# pin functional
PCICFG 53h PIO4 Direction 0=Input 1=Output PIO3 Direction 0=Input 1=Output PIO2 Direction 0=Input 1=Output
GPIO Select Register PIO1 Direction 0=Input 1=Output PIO0 Direction 0=Input 1=Output SMI# / PIO4 Select 0=SMI# (default) 1=PIO4 PME# / PIO3 Select 0=PME# (default) 1=PIO3
Default = 00h CLKRUN# / PIO2 Select 0=CLKRUN# (default) 1=PIO2 Default = 00h PIO2 Buffer 0=Disable 1=Enable PIO1 Buffer 0=Disable 1=Enable PIO0 Buffer 0=Disable 1=Enable
PCICFG 54h Reserved
GPIO Output Enable Register PIO4 Buffer 0=Disable 1=Enable PIO3 Buffer 0=Disable 1=Enable
These bits control buffer driving for those GPIO pins selected to be outputs. PCICFG 55h Reserved 0=Low 1=High GPIO Data Register PIO4 Data PIO3 Data 0=Low 1=High PIO2 Data 0=Low 1=High PIO1 Data 0=Low 1=High Default = 00h PIO0 Data 0=Low 1=High
For input pins these bits return the value presently being driven onto the pins; for output pins these bits select the level that will be driven. PCICFG 56h-7Bh PCICFG 7Ch Reserved Subsystem Vendor ID Restore Register - Byte 0 Default = 00h Default = 45h
The register is used to program the value of the Subsystem Vendor ID register at PCICFG 2Dh:2Ch. PCICFG 7Dh PCICFG 7Eh Subsystem Vendor ID Restore Register - Byte 1 Subsystem ID Restore Register - Byte 0 Default = 10h Default = 61h
The register is used to program the value of the Subsystem ID register at PCICFG 2Fh:2Eh. PCICFG 7Fh PCICFG 80h - EFh Subsystem ID Restore Register - Byte 1 Reserved Default = C8h Default = 00h
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7 PCICFG F0h 6 5 4 3 2 1 0 Default = 01h CAP_ID Register (RO)
This register returns a value of 01h to identify the Capabilities list item as being the PCI Power Management Register Block. PCICFG F1h Next_Item_Ptr Register (RO) Default = 00h
This register returns a value of 00h to indicate that there are no additional items in the Capabilities list. PCICFG F2h Reserved Device Specific Initialization (DSI): 0 = DSI is not required PCICFG F3h PME Support: 01000 = The PCI USB controller supports PME# generation from D3hot. PMC Register (RO) - Byte 0 Reserved Default = 01h
PME Clock: Version: 0 = PME# clock 001 = This function complies with Revision 1.0 of not required the PCI PowerManagement Interface Specification. to generate PME# Default = 40h D2 device state D1 device state support: support: 0 = No 0 = No Default = 00h PowerState (R/W): 00 = D0 01 = D1 (Not Supported) 10 = D2 (Not Supported) 11 = D3hot This field is used both to determine the current power state and to set a new power state. Unsupported states will be ignored when written to. Reserved
PMC Register (RO) - Byte 1
PCICFG F4h Reserved
PMCSR Register - Byte 0
PCICFG F5h PME Status (R/W): This bit is set when a PME event is generated. Write 1 to clear. Data_Scale (RO): 00 = Data register is not supported
PMCSR Register - Byte 1 Data_Select (RO): 0000 = Data register is not supported
Default = 00h PME_En (R/W): 0 = PME# assertion is disabled 1 = PME# is asserted when PME_ Status = 1
PCICFG F6h - FFh
Reserved
Default = 00h
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5.2 Host Controller Register Space
This register space is the operational control block in the USB core. It is responsible for the host controller operational states (Suspend, Disabled, Enabled), special USB signaling (Reset, Resume), status, interrupt control, and host controller configuration information. The host controller (HC) interface registers are PCI memory mapped I/O, hereafter referred to as MEMOFST. The bit formats for these registers are described in Table 5-2.
5.2.1
7
MEMOFST 00h-5Ch
6 5 4 3 2 1 0 Default = 10h Default = 000001h
MEMOFST 00h MEMOFST 01h-03h - Bits [7:0] - Bits [31:8] MEMOFST 04h HC Functional State: 00 = USB Reset 01 = USB Resume 10 = USB Operational 11 = USB Suspend The HC may force a state change from USB Suspend to USB Resume after detecting resume signaling from a downstream port. Processing of Bulk List: 0 = Disable 1 = Enable
HcRevision Register (RO)
Bits [31:0] correspond to: 00h = [7:0], 01h = [15:8], 02h = [23:16], 03h = [31:24] Revision - Indicates the Open HCI Specification revision number implemented by hardware (X.Y = XYh). FireLink support Specification 1.0. Reserved HcControl Register - Byte 0 Processing of Control List: 0 = Disable 1 = Enable Disable Isochronous List when Periodic List is enabled:(1) 0 = Yes 1 = No Processing of Periodic (interrupt and isochronous) List: 0 = Disable 1 = Enable The HC checks this bit prior to attempting any periodic transfers in a frame. Default = 00h Control Bulk Service Ratio: Specifies the number of control endpoints serviced for every bulk endpoint. Encoding is N1 where N is the number of control endpoints (i.e., 00 = 1 control endpoint; 11 = 4 control endpoints).
(1) Disabling the Isochronous List when the Periodic List is enabled allows interrupt endpoint descriptors to be serviced. While processing the Period List, the HC will check bit 3 when it finds an isochronous endpoint descriptor. MEMOFST 05h Reserved HcControl Register - Byte 1 Remote Wakeup Connected Enable: If a remote wakeup signal is supported, this bit is used to enable that operation. Since there is no remote wakeup signal supported, this bit is ignored. MEMOFST 06h-07h HcControl Register - Bytes 2 & 3 Reserved Remote Wakeup Connected (RO): Default = 00h Interrupt Routing: 0 = Interrupts routed to Indicates normal whether the HC interrupt supports a mechanism remote wakeup (INTA#) signal. This 1 = Interrupts implementation routed to does not SMI support any such signal. The bit is hardcoded to 0. Default = 00h
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7 MEMOFST 08h Reserved 6 5 4 3 2 1 0 Default = 00h Control List has an active endpoint descriptor?(1) 0 = No 1 = Yes HC Reset: Writing a 1 initiates a software reset. This bit is cleared by the HC upon completion of reset operation. HcCommandStatus Register - Byte 0 Ownership Change Request: When set by software, this bit sets the Ownership Change bit (MEMOFST 0Fh[6]). Cleared by software. (1) The bit may be set by either software or the HC. It is cleared by the HC each time it begins processing the head of the list (Bulk List for bit 2, Control List for bit 1) MEMOFST 09h HcCommandStatus Register - Byte 1 Reserved MEMOFST 0Ah HcCommandStatus Register - Byte 2 Reserved Default = 00h Schedule Overrun Count: This field increments every time the Scheduling Overrun bit (MEMOFST 0Ch[0] is set. The count wraps from 11 to 00. MEMOFST 0Bh HcCommandStatus Register - Byte 3 Reserved MEMOFST 0Ch Reserved Root Hub Status Change: This bit is set when the content of HcRh Status (50h53h) or the content of any HcRhPort Status Register (54h-5Bh) has changed. MEMOFST 0Dh-0Eh Frame Number Overflow: This bit is set when MEMOFST 3Ch[15] (Frame Number Register) changes from 0-to-1 or from 1-to-0. HcInterrupt Status Register - Byte 0* Unrecoverable Error: This event is not implemented and is hardcoded to 0. All writes are ignored. Resume Detected: This bit is set when the HC detects resume signaling on a downstream port. Start of Frame: This bit is set when the Frame Management block signals a "Start of Frame" event. Writeback Done Head: This bit is set after the Host Controller has written HcDoneHead to HccaDoneHead . Default = 00h Scheduling Overrun occurred? 0 = No 1 = Yes Default = 00h Default = 00h Bulk List has an active endpoint descriptor?(1) 0 = No 1 = Yes
HcInterruptStatus Register - Bytes 1 & 2 Reserved
Default = 00h
MEMOFST 0Fh Reserved Ownership Change: This bit is set when the Ownership Change Request bit (MEMOFST 08h[3]) is set.
HcInterruptStatus Register - Byte 3* Reserved
Default = 00h
* Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged.
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7 MEMOFST 10h Reserved Allow interrupt generation due to Root Hub Status Change: 0 = Ignore 1 = Enable MEMOFST 11h-12h 6 5 4 3 2 1 0 Default = 00h Allow interrupt generation due to Writeback Done Head: 0 = Ignore 1 = Enable Allow interrupt generation due to Scheduling Overrun: 0 = Ignore 1 = Enable Default = 00h HcInterruptEnable Register - Byte 0* Allow interrupt Reserved generation due All writes to this to Frame bit are ignored. Number Overflow: 0 = Ignore 1 = Enable Allow interrupt generation due to Resume Detected: 0 = Ignore 1 = Enable Allow interrupt generation due to Start of Frame: 0 = Ignore 1 = Enable
HcInterruptEnable Register - Bytes 1 & 2 Reserved
MEMOFST 13h Master interrupt generation: 0 = Ignore 1 = Allows all interrupts to be enabled in 10h-13h. Allow interrupt generation due to Ownership Change: 0 = Ignore 1 = Enable
HcInterruptEnable Register - Byte 3* Reserved
Default = 00h
* Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged. MEMOFST 14h Reserved Allow interrupt generation due to Root Hub Status Change: 0 = Ignore 1 = Disable MEMOFST 15h-16h HcInterruptDisable Register - Byte 0* Allow interrupt Reserved generation due All writes to this to Frame bit are ignored. Number Overflow: 0 = Ignore 1 = Disable Allow interrupt generation due to Resume Detected: 0 = Ignore 1 = Disable Allow interrupt generation due to Start of Frame: 0 = Ignore 1 = Disable Allow interrupt generation due to Writeback Done Head: 0 = Ignore 1 = Disable Default = 00h Allow interrupt generation due to Scheduling Overrun: 0 = Ignore 1 = Disable Default = 00h
HcInterruptDisable Register - Bytes 1 & 2 Reserved
MEMOFST 17h Master interrupt generation: 0 = Ignore 1 = Allows all interrupts to be disabled in 10h-13h. Allow interrupt generation due to Ownership Change: 0 = Ignore 1 = Disable
HcInterruptDisable Register - Byte 3* Reserved
Default = 00h
* Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged. MEMOFST 18h-1Bh HcHCCA Register Default = 00h
Bits [31:0] correspond to: 18h = [7:0], 19h = [15:8], 1Ah = [23:16], 1Bh = [31:24]. - Bits [7:0] Reserved - Bits [31:8] Pointer to HCCA base address MEMOFST 1Ch-1Fh HcPeriodCurrentED Register Default = 00h
Bits [31:0] correspond to: 1Ch = [7:0], 1Dh = [15:8], 1Eh = [23:16], 1Fh = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current Periodic List End Descriptor
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7 MEMOFST 20h-23h 6 5 4 3 2 1 0 Default = 00h HcControlHeadED Register Bits [31:0] correspond to: 20h = [7:0], 21h = [15:8], 22h = [23:16], 23h = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current Control List Head End Descriptor MEMOFST 24h-27h HcControlCurrent ED Default = 00h
Bits [31:0] correspond to: 24h = [7:0], 25h = [15:8], 26h = [23:16], 27h = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current End Descriptor in Control List MEMOFST 28h-2Bh HcBulkHeadED Register Default = 00h
Bits [31:0] correspond to: 28h = [7:0], 29h = [15:8], 2Ah = [23:16], 2Bh = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current Bulk List Head End Descriptor in Control List MEMOFST 2Ch-2Fh HcBulkCurrentED Register Default = 00h
Bits [31:0] correspond to: 2Ch = [7:0], 2Dh = [15:8], 2Eh = [23:16], 2Fh = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current Bulk List End Descriptor MEMOFST 30h-33h HcDoneHead Register Default = 00h
Bits [31:0] correspond to: 30h = [7:0], 31h = [15:8], 32h = [23:16], 33h = [31:24]. - Bits [3:0] Reserved - Bits [31:4] Pointer to current Done List Head End Descriptor MEMOFST 34h-37h - Bits [13:0] HcFmInterval Register Default = 2EDFh
Bits [31:0] correspond to: 34h = [7:0], 35h = [15:8], 36h = [23:16], 37h = [31:24]. Frame Interval - These bits specify the length of a frame as (bit times 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. (Default = 2EDFh) - Bits [15:14] Reserved - Bits [30:16] FS Largest Data Packet: These bits specify a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. - Bit 31 Frame Interval Toggle - This bit is toggled by HCD whenever it loads a new value into the Frame Interval bits (bits [13:0]). MEMOFST 38h-3Bh - Bits [13:0] HcFrameRemaining Register Default = 00h
Bits [31:0] correspond to: 38h = [7:0], 39h = [15:8], 3Ah = [23:16], 3Bh = [31:24]. Frame Remaining (RO) - This 14-bit decrementing counter is used to time a frame. When the HC is in the USB Operational state, the counter decrements each 12MHz clock period. When the count reaches 0, the end of a frame has been reached. The counter reloads with Frame Interval (MEMOFST 34h[13:0]) at that time. In addition, the counter loads when the HC transitions into the USB Operational state. - Bits [30:14] Reserved - Bit 31 Frame Remaining Toggle (RO) - This bit is loaded with Frame Interval Toggle (MEMOFST 34h[31]) when Frame Remaining (bits [13:0]) is loaded. HcFmNumber Register Default = 00h
MEMOFST 3Ch-3Fh - Bits [15:0]
Bits [31:0] correspond to: 3Ch = [7:0], 3Dh = [15:8], 3Eh = [23:16], 3Fh = [31:24]. Frame Number (RO) - This 16-bit incrementing counter is incremented coincident with the load of Frame Remaining (MEMOFST 38h[13:0]). The count will roll over from FFFh to 0h. - Bits [31:16] Reserved
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7 MEMOFST 40h-43h 6 5 4 3 2 1 0 Default = 00h HcPeriodicStart Register
Bits [31:0] correspond to: 40h = [7:0], 41h = [15:8], 42h = [23:16], 43h = [31:24]. - Bits [13:0] Periodic Start - These bits are used by the List Processor to determine where in a frame the Periodic List processing must begin. - Bits [31:14] Reserved MEMOFST 44h-47h - Bits [11:0] HcLSThreshold Register Default = 00h
Bits [31:0] correspond to: 44h = [7:0], 45h = [15:8], 46h = [23:16], 47h = [31:24]. LS Threshold - These bits contain a value used by the Frame Management Block to determine whether or not a low speed transaction can be started in the current frame. - Bits [31:12] Reserved MEMOFST 48h HcRhDescriptorA Register - Byte 0 (RO) Default = 02h
Number Downstream Ports - The USB core supports two downstream ports. MEMOFST 49h Reserved HcRhDescriptorA Register - Byte 1 No Overcurrent Protection:(1) 0 = Overcurrent status is reported 1 = Overcurrent status is not reported Over-current Protection Mode: 0 = Global overcurrent 1 = Individual OverCurrent This bit is only valid when bit 4 is cleared. This bit should be written to 0. (1) Bits 4 and 1 should be written to support the external system port over-current and switching implementations. MEMOFST 4Ah HcRhDescriptorA Register - Byte 2 Reserved MEMOFST 4Bh Power-On to Power-Good Time - The USB core power switching is effective within 2ms. The field value is represented as the number of 2ms intervals. This field should be written to support the system implementation. This field should always be written to a non-zero value. MEMOFST 4Ch-4Dh HcRhDescriptorB Register - Bytes 0 & 1 Default = 00h HcRhDescriptorA Register - Byte 3 Default = 01h Default = 00h Device Type (RO): The USB core is not a compound device. Default = 00h Power No Power Switching Switching:(1) Mode: 0 = Ports are 0 = Global powered switching switched 1 = Individual 1 = Ports are switching always powered on This bit is only valid when bit 1 is cleared. This bit should be written to 0.
Bits [15:0] correspond to: 4Ch = [7:0], 4Dh = [15:8]. - Bit 0 Reserved - Bits [15:1] Device Removable - USB core ports default to removable devices: 0 = Device not removable 1 = Device removable Bit 15 corresponds to Port 15, Bit 14 corresponds to Port 14, the remaining bits follow suit. Unimplemented ports are reserved.
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7 MEMOFST 4Eh-4Fh 6 5 4 3 2 1 0 Default = 00h HcRhDescriptorB Register- Bytes 2 & 3
Bits [15:0] correspond to: 4Eh = [7:0], 4Fh = [15:8]. - Bit 0 Reserved - Bits [15:1] Port Power Control Mask: Bit 15 corresponds to Port 15, Bit 14 corresponds to Port 14, the remaining bits follow suit. Unimplemented ports are reserved. 0 = Device not removable 1 = Global power mask This field is only valid if No Power Switching bit (MEMOFST 49h[1]) is cleared and Power Switching Mode Bit (MEMOFST 49h[0]) is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower, MEMOFST 54h[1:0] and 58h[1:0]). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower, MEMOFST 52h[0] and 50h[0]). MEMOFST 50h HcRhStatus Register - Byte 0 Reserved Over-current Indicator (RO):(1) Default = 00h Read: Local Power Status
Not supported. Reflects state of Always read 0. OVCR pin. Write: Clear 0 = No overGlobal Power current 0 = No effect condition 1 = Issue Clear 1 = OverGlobal current Power condition command to ports (1) Bit 1 is only valid if the No Over-current Protection (MEMOFST 49h[4]) and Over-current Protection Mode (MEMOFST 49h[3]) bits are cleared. MEMOFST 51h Read: Device Remote Wakeup Enable(1) 0 = Disabled 1 = Enabled Write: Set Remote Wakeup Enable 0 = No effect 1 = Sets Device Remote Wakeup Enable (1) Allows port Connect Status Change Bit (MEMOFST 56h[0] for Port 1 and MEMOFST 59h[0] for Port 2) as a remote wakeup event. HcRhStatus Register - Byte 1 Reserved Default = 00h
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7 MEMOFST 52h 6 5 4 3 2 1 0 Default = 00h Over-current Indicator Change This bit is set when the Overcurrent Indicator bit (MEMOFST 50h[1]) changes. Write 1 to clear Read: Local Power Status Change Not supported. Always read 0 Write: Set Global Power 0 = No effect 1 = Issue Set Global Power command to ports Default = 00h HcRhStatus Register - Byte 2 Reserved
MEMOFST 53h Clear Remote Wakeup Enable (WO) 0 = No effect 1 = Clear Device Remote Wakeup Enable bit (MEMOFST 51h[7]) MEMOFST 54h Reserved
HcRhStatus Register - Byte 3 Reserved
HcRhPort1Status Register - Byte 0 Read: Port Reset Status 0 = Port reset status signal not active 1 = Port reset signal active Write: Set Port Reset 0 = No effect 1 = Sets Port Reset Status Read: Port Over-current Indicator(1) 0 = No overcurrent condition 1 = Overcurrent condition Write: Clear Port Suspend 0 = No effect 1 = Initiates selective resume sequence for the port Read: Port Read: Port Suspend Status Enable Status 0 = Port is not suspended 1 = Port is selectively suspended Write: Set Port Suspend 0 = No effect 1 = Sets Port Suspend Status 0 = Port disabled 1 = Port enabled Write: Set Port Enable 0 = No effect 1 = Sets Port Enable Status
Default = 00h Read: Current Connect Status 0 = No device connected 1 = Device connected.( 2) Write: Clear Port Enable 0 = No effect 1 = Clears Port Enable Status bit (bit 1)
(1) The USB core supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This bit is only valid if the No Over-current Protection (MEMOFST 49h[4]) bit is cleared and Over-current Protection Mode (MEMOFST 49h[3]) bit is set. (2) If the Device Removable bits (MEMOFST 4Ch[15:0]) are set (not removable), bit 0 is always 1.
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7 MEMOFST 55h 6 5 4 3 2 1 0 Default = 00h Read: Low Speed Device Attached(1) 0 = Full speed device 1 = Low speed device Write: Clear Port Power 0 = No effect 1 = Clears Port Power Status (bit 0) Read: Port Power Status(2) 0 = Port power is off 1 = Port power is on Write: Set Port Power 0 = No effect 1 = Sets Port Power Status HcRhPort1Status Register - Byte 1 Reserved
(1) Bit 1 defines the speed (and bus idle) of the attached device. It is only valid when Current Connect Status (MEMOFST 54h[0]) bit is set. (2) Bit 0 reflects the power state of the port regardless of the power switching mode. If the No Power Switching (MEMOFST 49h[1]) bit is set, bit 0 is always read as 1. MEMOFST 56h Reserved HcRhPort1Status Register - Byte 2 Port Reset Status Change Port Overcurrent Indicator Change Port Suspend Status Change Indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed 1 = Port resume is complete Port Enable Status Change Indicates that the port has been disabled due to a hardware event (cleared Port Enable Status, MEMOFST 54h[1]). 0 = Port has not been disabled Default = 00h Connect Status Change
0 = Port reset is not This bit is set complete 1 = Port reset is when the Overcurrent complete Indicator (MEMOFST 50h[1]) bit changes. Write 1 to clear
Indicates a connect or disconnect event has been detected. 0 = No connect/dis connect event 1 = Hardware detection of connect/dis 1 = Port Enable connect Status has event(1) been Write 1 to clear cleared
(1) If the Device Removable Bits (MEMOFST 4Ch[15:1]) are set, bit 0 resets to 1. MEMOFST 57h HcRhPort1Status Register - Byte 3 Reserved Default = 00h
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7 MEMOFST 58h Reserved 6 5 4 3 2 1 0 Default = 00h Read: Current Connect Status 0 = No device connected 1 = Device connected.( 2) Write: Clear Port Enable 0 = No effect 1 = Clears Port Enable Status bit (bit 1) HcRhPort2Status Register - Byte 0 Read: Port Reset Status 0 = Port reset status signal not active 1 = Port reset signal active Write: Set Port Reset 0 = No effect 1 = Sets Port Reset Status Read: Port Over-current Indicator(1) 0 = No overcurrent condition 1 = Overcurrent condition Write: Clear Port Suspend 0 = No effect 1 = Initiates selective resume sequence for the port Read: Port Read: Port Suspend Status Enable Status 0 = Port is not suspended 1 = Port is selectively suspended Write: Set Port Suspend 0 = No effect 1 = Sets Port Suspend Status 0 = Port disabled 1 = Port enabled Write: Set Port Enable 0 = No effect 1 = Sets Port Enable Status
(1) The USB core supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This bit is only valid if the No Over-current Protection (MEMOFST 49h[4]) bit is cleared and Over-current Protection Mode (MEMOFST 49h[3]) bit is set. (2) If the Device Removable bits (MEMOFST 4Ch[15:0]) are set (not removable), bit 0 is always 1. MEMOFST 59h HcRhPort2Status Register - Byte 1 Reserved Read: Low Speed Device Attached(1) 0 = Full speed device 1 = Low speed device Write: Clear Port Power 0 = No effect 1 = Clears Port Power Status (bit 0) Default = 00h Read: Port Power Status(2) 0 = Port power is off 1 = Port power is on Write: Set Port Power 0 = No effect 1 = Sets Port Power Status
(1) Bit 1 defines the speed (and bus idle) of the attached device. It is only valid when Current Connect Status (MEMOFST 54h[0]) bit is set. (2) Bit 0 reflects the power state of the port regardless of the power switching mode. If the No Power Switching (MEMOFST 49h[1]) bit is set, bit 0 is always read as 1.
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7 MEMOFST 5Ah Reserved 6 5 4 3 2 1 0 Default = 00h Port Enable Status Change Indicates that the port has been disabled due to a hardware event (cleared Port Enable Status, MEMOFST 54h[1]). 0 = Port has not been disabled Connect Status Change HcRhPort2Status Register - Byte 2 Port Reset Status Change Port Overcurrent Indicator Change Port Suspend Status Change Indicates the completion of the selective resume sequence for the port. 0 = Port is not resumed 1 = Port resume is complete
0 = Port reset is not This bit is set complete 1 = Port reset is when the Overcurrent complete Indicator (MEMOFST 50h[1]) bit changes. Write 1 to clear
Indicates a connect or disconnect event has been detected. 0 = No connect/dis connect event 1 = Hardware detection of connect/dis 1 = Port Enable connect Status has event(1) been Write 1 to clear cleared
(1) If the Device Removable Bits (MEMOFST 4Ch[15:1]) are set, bit 0 resets to 1. MEMOFST 5Bh HcRhPort2 Status Register - Byte 3 Reserved Default = 00h
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5.2.2 Legacy Support Registers
Four registers are provided for legacy support: 1. HceControl - - Used to enable and control the emulation hardware and report various status information. 2. HceInput - - Emulation side of the legacy Input Buffer register. 3. HceOutput - - Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software. 4. HceStatus - - Emulation side of the legacy Status register. These registers are located in the Host Controller Register Space; from MEMOFST 100h through 10Fh. The bit formats for these registers are described in Table 5-3. Refer to "Legacy Support" section for information when accessing these registers when emulation is enabled.
5.2.3
7
MEMOFST 100h-1Fh (Legacy Support Registers)
6 5 4 3 2 1 0 Default = 00h Character Pending HC generates emulation interrupt when the Output Full bit (MEMOFST 10Ch[0]) = 0. Emulation Interrupt (RO) Emulation Enable
MEMOFST 100h IRQ12 Active Indicates that a positive transition of IRQ12 from kybrd controller has occurred. Writing a 1 clears this bit, while writing a 0 leaves it unchanged. IRQ1 Active Indicates that a positive transition of IRQ1 from kybrd controller has occurred. Writing a 1 clears this bit, while writing a 0 leaves it unchanged. GateA20 Sequence Set by HC when a data value of D1h is written to Port 64h. Cleared by HC on write to Port 64h of any value other than D1h.
HceControl Register - Byte 0 External IRQEn IRQ1 and IRQ12 from kybrd controller causes emulation interrupt: 0 = Disable 1 = Enable This bit is independent of the Emulation Enable bit (bit 0) setting. IRQEn If the Output Full bit (MEMOFST 10Ch[0]) = 1, HC generates IRQ1 or IRQ12.
A static decode HC is enabled of the emulation for legacy interrupt emulation? condition. 0 = No 1 = Yes(1)
If the Aux Output Full bit 0 = Disable 1 = Enable (MEMOFST 10Ch[5]) = 0, HC generates IRQ1; if = 1, HC generates IRQ12. 0 = Disable 1 = Enable
(1) The HC decodes accesses to Ports 60h/64h and generates IRQ1 and/or IRQ12 when appropriate. Additionally, the HC generates an emulation interrupt at appropriate times to invoke the emulation software. MEMOFST 101h HceControl Register - Byte 1 Reserved Default = 00h A20 State: Indicates current state of Gate A20 on kybrd controller. Used to compare against value written to Port 60h when GateA20 Sequence is active. MEMOFST 102h-103h HceControl Register - Bytes 2 & 3 Default = 00h
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7 6 5 4 Reserved MEMOFST 104h HceInput Register - Bytes 0 Default = 00h 3 2 1 0
Input Data: - I/O data that is written to Ports 60h and 64h is captured in this register. Note: Refer to Table 4-4, "Emulated Registers and Side Effects", if emulation is enabled. MEMOFST 105h-107h HceInput Register - Bytes 1-3 Reserved MEMOFST 108h HceOutput Register - Bytes 0 Default = 00h Default = 00h
Output Data: - This register hosts data that is returned when an I/O read of Port 60h is performed by application software. Note: Refer to Table 4-4, "Emulated Registers and Side Effects", if emulation is enabled.) MEMOFST 109h-10Bh HceOutput Register - Bytes 1-3 Reserved MEMOFST 10Ch Parity Indicates parity error on keyboard/mous e data. Time-out Aux Output Full Used to indicate a time-out Assert IRQ12 if Output Full bit (MEMOFST 10Ch[0]) = 1 and IRQEn bit (MEMOFST 100h[3]) = 1? 0 = No 1 = Yes HceStatus Register - Byte 0 Inhibit Switch Cmd Data Flag Nominally used as a system flag by software to indicate a warm or cold boot. Input Full HC sets this bit to 1 on an I/O write to Port 60h or 64h except for the case of a GateA20 Sequence. While set to 1 and emulation is enabled (MEMOFST 100h[0] = 1), an emulation interrupt condition exists. Reflects state of HC sets this bit the keyboard on I/O writes to inhibit switch: Ports 60h and 64h: 0 = Inhibited 1 = Not 0 = Port 60h inhibited 1 = Port 64h Default = 00h Output Full HC sets this bit to 0 on a read of Port 60h. While this bit is 0 and the Character Pending bit (MEMOFST 100h[2]) = 1, an emulation interrupt condition exists. Setting this bit to 1 will generate either IRQ1 or IRQ12 under certain conditions(1). Default = 00h
(1) If the IRQEn bit (MEMOFST 100h[3]) = 1 and Aux Output Full bit (MEMOFST 10Ch[5]) = 0: IRQ1 is generated. If the IRQEn bit (MEMOFST 100h[3]) = 1 and Aux Output Full bit (MEMOFST 10Ch[5]) = 1: IRQ12 is generated. Note: Refer to Table 4-4, "Emulated Registers and Side Effects", on page 18 if emulation is enabled. MEMOFST 10Dh-10Fh HceStatus Register - Bytes 1-3 Reserved Default = 00h
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6.0
Electrical Ratings
Stresses above those listed in the following tables may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied.
6.1
Absolute Maximum Ratings
Parameter Min 5.0 Volt Max not allowed VCC + 0.5 VCC + 0.5 +70 +125 -0.5 -0.5 0 -40 Min 3.3 Volt Max +4.0 VCC + 0.5 VCC + 0.5 +70 +125 V V V degrees C degrees C Unit
Symbol
VCC VI VO TOP TSTG
Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature
not allowed -0.5 -0.5 0 -40
6.2
DC Characteristics:
Parameter Input low Voltage Input high Voltage Output low Voltage Output high Voltage Input Leakage Current Tristate Leakage Current Input Capacitance Output Capacitance Power Supply Current: 3.3V Core +2.4 +10.0 +10.0 +10.0 +10.0 Min -0.5 +2.0 Max +0.8 +5.5 +0.4 Unit V V V V A A pF pF IOL = 4.0mA IOH = -1.6mA VIN = VCC Condition
VCC = 3.3V 5%, TA = 0C to +70C Symbol VIL VIH VOL VOH IIL IOZ CIN COUT ICC
Predicted: 100mA max during operation, 1mA max during Standby (all clocks stopped)
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6.3
6.3.1
Sym t100 t101 t102 t103 t104 t105
AC Characteristics (Preliminary)
PCI Bus AC Timings
Parameter C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# setup time to PCICLK rising C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# hold time from PCICLK rising C/BE[3:0]#, AD[31:0], FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, LOCK#, PAR, SERR#, PERR# valid delay from PCICLK rising REQ# setup time to PCICLK rising REQ# hold time from PCICLK rising GNT# valid delay from PCICLK rising Setup Timing Waveform
50ns 100ns
Min 7 0 2 12 0 2
Max
Unit ns ns
Figure 6-1 6-2 6-3 6-1 6-2 6-3
11
ns ns ns
12
ns
Figure 6-1
0ns PCICLK
t100, t103 SIGNAL
Figure 6-2
0ns
Hold Timing Waveform
50ns 100ns
PCICLK t101, t104 SIGNAL
Figure 6-3
0ns PCICLK
Output Delay Timing Waveform
50ns 100ns
t102, t105 SIGNAL
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6.3.2
Sym
USB AC Timings: Full Speed Source
Parameter Min Max Unit Figure Condition (Notes 1, 2, and 3)
Driver Characteristics tR tF tRFM vCRS zDRV Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Driver Output Resistance CL = 50pF, Notes 5 and 6 4 4 90 1.3 28 20 20 110 2.0 43 ns ns % V ohm Steady state drive (tR/tF)
Data Source Timings tDRATE tFRAME tDJ1 tDJ2 tEOPT tDEOP tJR1 tJR2 tEOPR1 tEOPR2 Full Speed Data Rate Frame Interval Source Differential Driver Jitter: To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance: To Next Transition For Paired Transitions EOP Width at Receiver: Must Reject at EOP Must Accept as EOP 11.97 12.03 Mb/s ms ns ns ns ns ns ns Note 8 40 82 ns ns Note 8 Note 8 Note 8 -18.5 -9 18.5 9 Average bit rate = 12Mb/s 0.25% 1.0ms 0.05% Notes 7 and 8 -3.5 -4.0 160 -2 3.5 4.0 175 5
0.9995 1.0005
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FireLink USB 82C862
6.3.3
Sym
USB AC Timings: Low Speed Source
Parameter Min Max Unit Figure Condition (Notes 1, 2, and 4)
Driver Characteristics tR tF tRFM vCRS Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage 75 75 80 1.3 300 300 120 2.0 ns ns % V Notes 5 and 6 Min# measured with: CL = 50pF Max# measured with: CL = 350pF (tR/tF)
Data Source Timings tDRATE Low Speed Data Rate Source Differential Driver Jitter, At Host (Downstream): To Next Transition For Paired Transitions Source Differential Driver Jitter, At Function (Upstream): To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance, At Host (Upstream): To Next Transition For Paired Transitions Receiver Data Jitter Tolerance, At Function (Downstream): To Next Transition For Paired Transitions 1.4775 1.5225 Mb/s Average bit rate = 1.5Mb/s 1.5% Notes 7 and 8 -75 -45 75 45 ns ns Notes 7 and 8 -95 -150 1.25 -40 95 150 150 100 ns ns s ns 6-5 6-5 6-6 -152 -200 152 200 ns ns 6-6 -75 -45 75 45 ns ns Note 8 Note 8
tDDJ1 tDDJ2
tUDJ1 tUDJ2 tEOPT tDEOP
tUJR1 tUJR2
tDJR1 tDJR2
EOP Width at Receiver: 6-6 Note 8 tEOPR1 Must Reject at EOP 330 ns tEOPR2 Must Accept as EOP 675 ns Notes: 1. All voltages measured from the local ground potential, unless otherwise specified. 2. All timings use a capacitive load (CL) to ground of 50pF, unless otherwise specified. 3. Full speed timings have a 1.5 kohm pull-up to 2.8V on the D+ data line. 4. Low speed timings have a 1.5 kohm pull-up to 2.8V on the D- line. 5. Measured from 10% to 90% of the data signal. 6. The rising and falling edges should be smoothly transitioning (monotonic). 7. Timing difference between the differential data signals. 8. Measured at crossover point of differential data signals. 9. The maximum load specification is the maximum effective capacitive load allowed that meets the target hub Vbus droop of 330mV.
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FireLink USB 82C862
Figure 6-4
tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N * tP ERIOD + tX JR1 Paired Transitions N * tP ERIOD + tX JR2
Differential Data Jitter
Figure 6-5
tPERIOD Differential Data Lines
Differential to EOP Transition Skew and EOP Width
Crossover Point Extended
Crossover Point Differential Data to SE0 Skew N * tPERIOD + tDEOP
Source EOP Width: tEOPT Source EOP Width: tEOP1, tEOP2
Figure 6-6
tPERIOD Differential Data Lines
Receiver Jitter Tolerance
tJR
tJR1
t JR2
Consecutive Transitions N * tPERIOD + tJR1 Paired Transitions N * tPERIOD + tJR2
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FireLink USB 82C862
7.0 Mechanical Package Outlines
100-Pin Low-Profile Quad Flat Pack (LQFP)
Figure 3.
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FireLink USB 82C862
8.0 NAND Tree Test Mode
The NAND tree mode tests both input and bi-directional pins that are part of the NAND tree chain. The NAND tree chain starts at pin 21 (TEST0) while the output of the chain is at pin 4 (AD0). To enable the NAND tree test mode, strap FireLink 2.0 by pulling up the following pins during the rising edge of RESET#: Pin 25 (TEST1) and Pin 21 (TEST0). For reliable strapping, toggle PCICLK at least two times after RESET# goes low, and at least two times after RESET# goes high. After that strapping sequence, set both RESET# and PCICLK high. Do not toggle RESET# and PCICLK during the NAND tree test. Once in NAND tree mode, all pins together form the inputs to a NAND gate, with AD0 becoming the output of the NAND gate.
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